Review on Area Efficient CORDIC Algorithm and Reduction in Scale Factor

Supriya Aggarwal, Pramod K. Meher, and Kavita Khare proposed an area-time efficient CORDIC algorithm that completely eliminates the scale-factor by microrotation selection which is done by the most significant one detector in the micro rotation sequence generation circuit. Proper order of approximation of Taylor series is selected to meet the accuracy requirement, and the desired range of convergence is achieved. [1]. Francisco J. Jaime et al. proposed a new CORDIC algorithm, they show an enhanced version of the scaling-free CORDIC algorithm. Booth recoding algorithm is used to eliminate scaling and domain folding is avoided which reduces scaling to minimum but not eliminate it[2]. Leena Vachhani et al. proposed two areaefficient algorithms and their architectures based on CORDIC. Both the algorithms are applicable to the range of angles from 0 to 2 pi , and both the rotation and vectoring modes are used. Xilinx Spartan XC2S200E device is used and have the slice-delay products of about three.[3]. Koushik Maharatna et al. proposed a CORDIC rotator algorithm that which has the range of convergence from 0 to 2pi , and the target angle converges by executing appropriate iteration steps while keeping the scale factor virtually constant and completely predictable using the domain folding method. The IHP in-house 0.25m BiCMOS technology device is used on Synopsys' design analyzer and slice delay product of 26.98 is achieved[4].